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| INTEGRATED CIRCUITS HSTL16918 9-bit to 18-bit HSTL-to-LVTTL memory address latch Product data 2001 Jun 16 Philips Semiconductors Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 FEATURES * Inputs meet JEDEC HSTL Std. JESD 8-6, and outputs meet Level III specifications PIN CONFIGURATION 2Q1 1Q1 GND D1 D2 VCC D3 1 2 3 4 5 6 7 8 9 48 VCC 47 VCC 46 1Q2 45 2Q2 44 GND 43 1Q3 42 2Q3 41 VCC 40 1Q4 39 2Q4 38 GND 37 1Q5 36 2Q5 35 GND 34 1Q6 33 2Q6 32 VCC 31 1Q7 30 2Q7 29 GND 28 1Q8 27 2Q8 26 VCC 25 VCC * ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. * Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA. * Packaged in 48-pin plastic thin shrink small outline package (TSSOP48) DESCRIPTION The HSTL16918 is a 9-bit to 18-bit D-type latch designed for 3.15 to 3.45 V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels. The HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE) input. Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is LOW the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken HIGH, the Q outputs are latched at the levels set up at the D inputs. The HSTL16918 is characterized for operation from 0 to +70 C. D4 GND 1LE 10 GND 11 VREF 12 GND 13 2LE 14 GND 15 D5 16 D6 17 D7 18 VCC 19 D8 20 D9 21 GND 22 2Q9 23 1Q9 24 SW00768 ORDERING INFORMATION PACKAGES 48-pin plastic thin shrink small outline package (TSSOP48) TEMPERATURE RANGE 0 to +70 C ORDER CODE HSTL16918DGG DWG NUMBER SOT362-1 2001 Jun 16 2 853-2258 26484 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 PIN DESCRIPTION PIN 4, 5, 7, 8, 16, 17, 18, 20, 21 2, 46, 43, 40, 37, 34, 31, 28, 24 1, 45, 42, 39, 36, 33, 30, 27, 23 10 14 12 6, 19, 25, 26, 32, 41, 47, 48 3, 9, 11, 13, 15, 22, 29, 35, 38, 44 SYMBOL D[1-9] 1Q[1-9] Outputs 2Q[1-9] Inputs FUNCTION LOGIC DIAGRAM (positive logic) VREF 12 1LE D1 10 4 1D 2 C1 1Q1 1LE 2LE VREF VCC GND Latch enable Reference voltage Supply voltage Ground 2LE 14 1D 1 C1 2Q1 TO EIGHT OTHER CHANNELS SW00769 FUNCTION TABLE INPUTS LE L L H D H L X OUTPUT Q H L Q0 1 NOTE: 1. Output level before the indicated steady-state input conditions were established. 2001 Jun 16 3 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 ABSOLUTE MAXIMUM RATINGS1 Over operating free-air temperature range (unless otherwise noted). SYMBOL VCC VI VO IIK IOK IO JA Tstg PARAMETER Supply voltage range Input voltage range 2 2 CONDITIONS RATING -0.5 to +4.6 -0.5 to VCC +0.5 -0.5 to VCC +0.5 UNIT V V V mA mA mA mA C/W C Output voltage range Input clamp current VI < 0 VO < 0 or VO > VCC VO = 0 to VCC -50 50 50 100 89 -65 to +150 Output clamp current 3 Continuous output current Continuous current through each VCC or GND Package thermal impedance 4 Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This current flows only when the output is in the high state and VO > VCC. 4. The package thermal impedance is calculated in accordance with JESD 51. RECOMMENDED OPERATING CONDITIONS1 LIMITS SYMBOL VCC VREF VI VIH VIL VIH VIL IOH IOL Tamb Supply voltage Reference voltage Input voltage AC high-level input voltage AC low-level input voltage DC high-level input voltage DC low-level input voltage High-level output current Low-level output current Operating free-air temperature range 0 All inputs All inputs All inputs All inputs VREF + 100 mV VREF - 100 mV -24 24 +70 PARAMETER Min 3.15 0.68 0 VREF + 200 mV VREF - 200 mV 0.75 Nom Max 3.45 0.9 1.5 UNIT V V V V V V V mA mA C NOTE: 1. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. 2001 Jun 16 4 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted). LIMITS SYMBOL VIK VOH VOL Control inputs II Data inputs VREF ICC Control inputs CI CO Data inputs Outputs PARAMETER TEST CONDITIONS VCC = 3.15 V; II = -18 mA VCC = 3.15 V; IOH = -24 mA VCC = 3.15 V; IOL = 24 mA VCC = 3.45 V; VI = 0 or 1.5 V VCC = 3.45 V; VI = 0 or 1.5 V VCC = 3.45 V; VREF = 0.68 V or 0.9 V VCC = 3.45 V; VI = 0 or 1.5 V VCC = 0 or 3.3 V; VI = 0 or 3.3 V VCC = 0 or 3.3 V; VI = 0 or 3.3 V VCC = 0 V; VO = 0 V 50 2 2.5 4 2.4 0.5 5 5 90 100 Min Typ 1 Max -1.2 UNIT V V V A A A mA pF pF pF NOTE: 1. All typical values are at VCC = 3.3 V; Tamb = 25 C. TIMING REQUIREMENTS Over recommended operating free-air temperature range (unless otherwise noted). SYMBOL tw tsu th tldr PARAMETER Pulse duration Setup time Hold time Data race condition time 1 TEST CONDITIONS LE LOW (Figure 1) D before LE (Figure 2) D after LE (Figure 2) D after LE VCC = 3.3 V 0.15 V Min 3 2 1 0 Max UNIT ns ns ns ns NOTE: 1. This is the maximum time after LE switches LOW that the data input can return to the latched state from the opposite state without producing a glitch on the output. SWITCHING CHARACTERISTICS Over recommended operating free-air temperature range; VREF = 0.75 V. SYMBOL PARAMETER FROM (INPUT) D tpd Propagation delay (Figure 3) LE Q 1.9 4.2 ns TO (OUTPUT) Q VCC = 3.3 V 0.15 V Min 1.9 Max 3.4 ns UNIT SIMULTANEOUS SWITCHING CHARACTERISTICS Over recommended operating free-air temperature range; VREF = 0.75 V SYMBOL PARAMETER FROM (INPUT) D LE TO (OUTPUT) Q Q VCC = 3.3 V 0.15 V Min 1.9 1.9 Max 4.4 5.2 ns ns UNIT tpd Propagation delay; all outputs switching g y g (Figure 3) 2001 Jun 16 5 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 VOLTAGE WAVEFORMS tw INPUT VREF VREF 0.25 V LOAD CIRCUIT FROM OUTPUT UNDER TEST CL = 80 PF (see Note) 500 1.25 V SW00770 SW00773 Figure 1. Pulse duration NOTE: CL includes probe and jig capacitance. Figure 4. Load circuit 1.25 V LE VREF 0.25 V tsu th 1.25 V DATA INPUT VREF VREF 0.25 V SW00771 Figure 2. Setup and Hold times 1.25 V INPUT (Note 1) VREF tPLH VREF 0.25 V tPHL VOH OUTPUT 1.5 V 1.5 V VOL SW00772 Figure 3. Propagation delay times NOTES: 1. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 1 ns, tf 1 ns. 2. The outputs are measured one at a time with one transition per measurement. 3. tPHL and tPLH are the same as tpd. 2001 Jun 16 6 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 2001 Jun 16 7 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 Data sheet status Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Date of release: 06-01 Document order number: 9397 750 08474 Philips Semiconductors 2001 Jun 16 8 |
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